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AS1322
Datasheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
SW 1
6 VIN
GND 2
AS1322
5
VOUT
4.1 Pin Descriptions
Table 2. Pin Descriptions
FB 3
4 SHDNN
Pin Number
1
2
3
4
5
6
Pin Name
SW
GND
FB
SHDNN
VOUT
VIN
Description
Switch Pin . Connect an inductor between this pin and V IN . Keep the PCB trace lengths as
short and wide as is practical to reduce EMI and voltage overshoot. If the inductor current
falls to zero, or pin SHDNN is low, an internal 100 ? anti-ringing switch is connected from this
pin to V IN to minimize EMI.
Note: An optional Schottky diode can be connected between this pin and V OUT .
Signal and Power Ground . Provide a short, direct PCB path between this pin and the
negative side of the output capacitor(s).
Feedback Pin . Feedback input to the g m error amplifier. Connect a resistor divider tap to this
pin. The output voltage can be adjusted from 2.5 to 5V by: V OUT = 1.23V[1 + (R 1 /R 2 )]
Shutdown Pin . Logic controlled shutdown input.
1 = Normal operation, 1.2MHz typical operating frequency.
0 = Shutdown; quiescent current <1μA. If SHDNN is undefined, pin SW may ring.
Note: In a typical application, SHDNN should be connected to V IN through a 1M ? pull-up
resistor.
Output Voltage Sense Input and Drain of the Internal PMOS Synchronous Rectifier .
Bias is derived from V OUT when V OUT exceeds V IN . PCB trace length from V OUT to the
output filter capacitor(s) should be as short and wide as is practical. V OUT is held at
approximately V IN - 0.6V during shutdown.
Input Voltage . The AS1322 gets its start-up bias from V IN unless V OUT exceeds V IN , in
which case the bias is derived from V OUT . Thus, once started, operation is completely
independent from V IN . Operation is only limited by the output power level and the internal
series resistance of the supply.
www.ams.com/DC-DC_Step-Up/AS1322
Revision 1.10
2 - 18
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